Exemplary embodiments of the present invention relate to a delay locked loop.
In general, a clock signal for matching the operation timings of various elements is used in a variety of systems and circuits. At this time, when the clock signal is inputted from the outside of an element and is used inside, time delay which is referred to as a skew may be caused by internal circuits of the element. A delay locked loop is used to compensate for such a skew so that an internal clock signal has the same phase as that of the external clock signal.
FIG. 1 is a simple configuration diagram of a conventional delay locked loop. The conventional delay locked loop includes a delay unit 101, a replica delay unit 103, and a delay information generation unit 105.
Referring to FIG. 1, an operation in which the conventional delay locked loop generates an output clock is described as follows.
The delay unit 101 is configured to delay an input clock signal CLK_IN and generate an output clock signal CLK_OUT. In general, the delay unit 101 includes a plurality of delay cells, each of which delays the input clock signal CLK_IN by a unit delay amount.
The replica delay unit 103 has a delay value obtained by modeling delay components through which the output clock signal CLK_OUT of the delay locked loop is to pass inside a system, and is configured to generate a feedback clock signal CLK_FB by delaying the output clock signal CLK_OUT by such a delay value.
The delay information generation unit 105 is configured to measure a phase difference between the input clock signal CLK_IN and the feedback clock signal CLK_FB and generate delay information D[1:N] based on the measured phase difference such that the delay unit 101 may have a proper delay value. When the delay unit 101 includes N delay cells, the delay information may have N-bit delay information.
The delay unit 101 decides the proper delay value according to the delay information received from the delay information generation unit 105, and generates an output clock CLK_OUT once again.
Through such an operation, the internal clock signal of a memory or the like, which is provided through the delay locked loop, is controlled so as to have the same phase as that of the external clock signal.
In general, the delay locked loop operates at a constant cycle. That is, the delay locked loop periodically repeats a process in which the delay information generation unit 105 detects a relative phase between the input clock signal CLK_IN and the feedback clock signal CLK_FB and the delay unit 101 uses the detection result to generate a new output clock signal CLK_OUT. Through this process, the output clock signal CLK_OUT may be changed depending on the input clock signal CLK_IN or a variation of an external environment, for example, a variation in an internal delay value of the system caused by a temperature change inside the circuit.
However, if the output clock signal CLK_OUT is changed according to periodic update of the delay value even while the output clock signal CLK_OUT of the delay locked loop is used, a data loss or duplication phenomenon may occur. In such a case, data processing may be unstable.